1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device which can simultaneously perform a read access and a write access independently.
2. Background of the Related Art
A semiconductor memory device can be largely classified into a random access memory (RAM) and a read only memory (ROM). The RAM is divided into a dynamic RAM in which one transistor and one capacitor constitute one unit cell and a static RAM which six transistors or four transistors and two load resistors constitute one unit cell. The dynamic RAM efficient in integration and fabrication is widely used in various fields including a main memory of a computer, etc.
FIG. 1 is a schematic block diagram showing the construction of a semiconductor memory device according to a prior art.
Referring to FIG. 1, the semiconductor memory device includes a bank 100 having a row address decoder and a column address decoder, a command controller 200 and a data input/output buffer 300. The command controller 200 receives a plurality of command signals RAS, CAS, WE, CS, CKE, CK, etc., from the outside so as to control the operations performed in the bank 100, such as, for example, read, write, refresh, etc. The bank 100 reads and outputs data of a unit cell corresponding to an address input thereto, or writes the data being input in the unit cell. Also, the data input/output buffer 300 buffers the data which is inputted/outputted to/from the bank 100 and inputs/outputs the buffered data from/to the outside.
A typical semiconductor memory device includes a plurality of banks, for example four banks. Since the respective banks have the same structure, only one bank 100 is shown in FIG. 1 for the sake of simplicity.
In addition, in FIG. 1, there are shown a minimum number of blocks necessary for explanation of the present invention among a plurality of blocks included in the semiconductor memory device.
A bank 100 includes eight segments 120a to 120h each having a plurality cell blocks and input/output sense amplifying units 110 and 130 for amplifying data outputted from the segments 120a to 120h for application to the data input/output buffer 300 or applying data inputted thereto from the data input/output buffer 300 to the segments 120a to 120h. 
A segment (for example, reference numeral 120a) includes a row address decoder 121 for decoding a row address to output the decoded row address, a column address decoder 122 for decoding a column address to output the decoded column address, and a cell region 120a_1 composed of a plurality of unit cells, and adapted to receive the decoded row address from the row address decoder 121 and the decoded column address from the column address decoder 122. The cell region 120a_1 includes a plurality of cell blocks 124a to 124h each having a plurality of unit cells and a plurality of bit line sense amplifying units 123a to 123i alternately arranged between the cell blocks 124a to 124h so as to sense and amplify data outputted from the cell blocks.
The semiconductor memory device shown in FIG. 1 exemplifies a memory having a capacity of 256 Mb. In case where the semiconductor memory device consists of four banks, each bank has a capacity of 64 Mb. Each bank can consist of, for example, a total of eight segments, each of which has a capacity of 8 Mb. A segment (for example, reference numeral 120a) includes a total of eight cell blocks 124a to 124h. A cell block (for example, reference numeral 124a) includes 256 word lines WL and 4 K (4*1024) bit lines BL. In addition, each cell block includes 256*4 K unit cells. It is assumed that a segment has a capacity of 8 Mb and each of the eight cell blocks includes 256 word lines as described above.
FIG. 2 is a circuit diagram showing one example of a bit line sense amplifying unit and a cell block shown in FIG. 1.
Particularly, FIG. 2 partially shows a first cell block 124a and a second cell block 124b, and a bit line sense amplifying unit 123b. 
Referring to FIG. 2, the first cell block 124a includes 256*4 K unit cells each consisting of a MOS transistor and a capacitor. Each of the word lines WL is connected to a gate terminal of each MOS transistor constituting each unit cell, and each of the bit lines BL is connected to a drain terminal of the MOS transistor constituting each unit cell while intersecting each of the bit lines BL and /BL. Each MOS transistor constituting a unit cell is connected at a source terminal thereof to one side of each capacitor constituting each unit cell, and the other side of each capacitor is connected to a cell plate power source (for example, ground power source). Although not shown, the second cell block 124b also has the same construction as that of the first cell block 124a. 
The bit line sense amplifying unit 123b includes a bit line sense amplifier 123b_4, a precharger 123b_3, an equalizer 123b_2, a data output part 123b_5 and connection parts 123b_1 and 123b_6. The bit line sense amplifier 123b_4 is enabled in response to bit line sense amplifier enable signals RTO and /S to thereby to amplify a difference between signals applied to the bit lines (for example, BL0 and /BL0). The precharger 123b_3 is enabled in response to a precharge enable signal BLEQ′ outputted when the bit line sense amplifier 123b_4 is disabled to thereby to precharge the bit lines (for example, BL0 and /BL0) with a bit line precharge voltage Vblp. The equalizer 123b_2 is enabled in response to an equalization signal BLEQ to thereby allow the voltage levels of a pair of bit lines (for example, BL0 and /BL0) connected to the first cell block 124a to be equal to each other. The data output part 123b_5 serves to output a data signal amplified by the bit line sense amplifier 123b_4 in response to a column control signal (for example, CDO) generated by a column address, to data lines DB0 and /DB0. Also, the connection parts 123b_1 and 123b_6 serves to selectively connect the bit line sense amplifier 123b_4 to the cell blocks 124a and 124b adjacent to the bit line sense amplifying unit 123b. 
In this case, the number of bit line sense amplifiers included in the bit line sense amplifying unit 123b is determined depending on the number of bit line pairs included in adjacent cell blocks, and the bit line sense amplifying unit 123b is connected to the first cell block 124a or the second cell block 124b in response to sense amplifier connecting signals BISH and BISL. Although not shown in FIG. 2, the bit line pairs BL1 and /BL1 in 124a are connected to a bit line sense amplifier included in the bit line sense amplifying unit 123a and BL1 and /BL1 in 124b are connected to a bit line sense amplifier included in the bit line sense amplifying unit 124b. 
In order to read data from the cell blocks in the conventional semiconductor memory device shown in FIGS. 1 and 2, it is required that the word lines should be first enabled and data of the cell block connected to the enabled word lines should be then outputted to the data line. In the meantime, in order to write data in a cell block, it is required that the word lines are enabled and data provided through the data line should be then written in the cell block connected to the enabled word lines. However, the semiconductor memory device according to such a conventional prior art entails a problem in that since data is written or read in or from the cell block through the data line according to the access mode, a write access and a read access cannot be simultaneously performed independently.